A 0.1 /spl mu/m CMOS technology with tilt-implanted punchthrough stopper (TIPS)

A 0.1-/spl mu/m CMOS technology with tilt-implanted punchthrough stopper (TIPS) structure is proposed. By taking advantage of large-angle-tilt implant, the p/sup -/ and n/sup -/ TIPS pocket regions are successfully realized adjacent to the n/sup -/ LDD region and p/sup +/ source/drain without increasing impurity concentration under the n/sup +/ and p/sup +/ source/drain junctions for n- and p-FETs, respectively. In spite of the low 10/sup 16/cm/sup -3/-order substrate doping, deep 0.15-0.2 /spl mu/m source/drain, and practically thick 6-nm gate oxides, the TIPS n- and p-FETs are for the first time demonstrated to achieve high punchthrough resistance with suppressed body effect and junction capacitance, at least, down to 0.12 /spl mu/m and 20-40%, improved switching speed of 20 ps unlike conventional FETs, while maintaining full compatibility with the conventional CMOS process. The TIPS n- and p-FETs also exhibit suppressed hot-carrier-induced degradation due to the confined impurity profiles. The TIPS technology is most promising for 0.1-/spl mu/m CMOS ULSIs.<>