DocumentCode
2528699
Title
A 372 ps 64-bit adder using fast pull-up logic in 0.18-/spl mu/m CMOS
Author
Kim, Jooyoung ; Lee, Kangmin ; Yoo, Hoi-Jun
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon
fYear
2006
fDate
21-24 May 2006
Lastpage
16
Abstract
This paper presents a 372 ps 64-bit adder using fast pull-up logic (FPL) in 0.18 mum CMOS technology. Fast pull-up logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372 ps. The adder has a modified tree architecture using load distribution method and has 6 logic stages
Keywords
CMOS logic circuits; adders; delay circuits; 0.18 micron; 372 ps; 64 bit; CMOS logic circuit; FPL; domino-static adder; fast pull-up logic; load distribution; logic stages; modified tree architecture; Arithmetic; CMOS logic circuits; CMOS technology; Delay effects; MOSFETs; Microprocessors; Paper technology; Propagation delay; Signal generators; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1692510
Filename
1692510
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