A second-generation single-chip stereo imager

Author

Philipp, Ralf M. ; Etienne-Cummings, Ralph

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD

fYear

2006

fDate

21-24 May 2006

Lastpage

220

Abstract

A second-generation stereo vision chip, fabricated in a 0.35mum 4M2P CMOS process and incorporating two 128 times 128 pixel linear current-mode imagers and current-mode disparity computation circuitry, is presented. Parallel computation of the sum-of-absolute-difference matching metric allows the chip to produce 114 times 124 pixel depth maps at 30 frames per second, performing 2.2 billion operations per second, while using 10.1mA from a 3.3V supply

Keywords

CMOS digital integrated circuits; CMOS image sensors; current-mode circuits; stereo image processing; 0.35 micron; 10.1 mA; 114 pixel; 124 pixel; 128 pixel; 14136 pixels; 16384 pixels; 3.3 V; CMOS process; current-mode imagers; disparity computation circuitry; stereo vision chip; sum-of-absolute-difference matching; CMOS process; Circuits; Computer vision; Energy consumption; Finite impulse response filter; Layout; Optical filters; Optical noise; Pixel; Stereo vision;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692561

Filename

1692561

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2529739