Register size vs. fault coverage in modified circular built-in self-test

Author

Stroud, Charles E. ; He, Ping ; Damarla, T. Raju

Author_Institution

Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA

fYear

1996

fDate

16-19 Sep 1996

Firstpage

23

Lastpage

28

Abstract

Improvement in the effectiveness of circular built-in self-test (BIST) in practical applications is achieved by adding a shift register in the BIST chain with additional logic for deterministic pattern generation. The designer can increase the size of this additional register called the target register, to increase the cycle length of the state transition graph of the circuit in the BIST mode of operation for increased fault coverage. Design guidelines are given to assist in determining which circuits will be good candidates for this BIST approach

Keywords

application specific integrated circuits; built-in self test; fault diagnosis; logic testing; shift registers; BIST; BIST mode; additional register; cycle length; design guidelines; deterministic pattern generation; effectiveness; fault coverage; modified circular built-in self-test; shift register; target register; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Flip-flops; Helium; Logic; Sequential circuits; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON '96, Test Technology and Commercialization. Conference Record

Conference_Location

Dayton, OH

ISSN

1088-7725

Print_ISBN

0-7803-3379-9

Type

conf

DOI

10.1109/AUTEST.1996.547672

Filename

547672