Modified scan architecture for an effective scan testing

Latest VLSI circuits face the problem of power dissipation not only in design phase but also during testing phase. Power dissipation during testing may be increased up to three times more than that during normal operation. Testing power, testing time and test area overhead are the critical parameters to be optimized for large and complex VLSI circuits. Scan architectures are widely used in testing of sequential circuits. In this paper, modified scan architecture is proposed to reduce shift and capture power, testing time and test area overhead in scan testing. The scan architecture is modified such that the number of transitions during shift and capture process is reduced. Modification is carried out by eliminating an inverter in the serial path of scan latch. Hence the scan cell not only reduces the power but also reduces the test area overhead and critical path delay in scan chain. The reduction in critical path delay of scan cell improves the speed during testing process and normal operation of circuit. The experimental results with benchmark circuits (ISCAS 89) show that a favorable reduction is achieved in the shifting and capture power, test area overhead and critical path delay.