Optimization of a sigma-delta modulator by the use of a slow ADC

A 1-bit sigma-delta modulator with a loop delay t/sub dl/ (conversion time of the analog-to-digital converter, or ADC) is considered. Its idle channel pattern, which is calculated by using the modified z-transform, is influenced by the loop delay time. An optimization of this delay time yields a minimized signal power at the input of the quantizer and an improved signal-to-noise ratio at the output of the sigma-delta modulator. Optimum performance is achieved for t/sub dl/=0.25 (T=sample period). Numerous simulations verify these results. It is concluded that the use of a slow ADC can be advantageous.<>