Design issues for Dynamic Voltage Scaling

Author

Burd, Thomas D. ; Brodersen, Robert W.

Author_Institution

Wireless Res. Center, California Univ., Berkeley, CA, USA

fYear

2000

fDate

2000

Firstpage

9

Lastpage

14

Abstract

Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the processor´s supply voltage so that it consumes the minimal amount of energy by operating at the minimum performance level required by the active software processes. A dynamically varying supply voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability.

Keywords

CMOS digital integrated circuits; circuit feedback; computer power supplies; delays; integrated circuit design; logic design; CMOS; SRAM; circuit delay; computational load; design flow; dynamic logic; dynamic voltage scaling; dynamically varying supply voltage; energy efficiency; minimum performance level; noise; portable electronic devices; processor circuit design; time-varying performance; CMOS logic circuits; Circuit synthesis; Clocks; Dynamic voltage scaling; Energy consumption; Energy efficiency; Logic design; Microprocessors; Prototypes; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on

Print_ISBN

1-58113-190-9

Type

conf

DOI

10.1109/LPE.2000.155245

Filename

876749