Hardware performance analysis of a parametric CORDIC IP

In this paper, a parametric CORDIC IP is presented, implementing fixed point arithmetic (sine, cosine, and arctangent) trigonometric functions evaluation. The VHDL design uses parameters to define the bitwidth and the precision of the input and output signals. Important design options for hardware implementation include iterative, unrolled and unrolled pipelined architectures of the CORDIC module. The design uses the VHDL ´93 backwards-compatible version of the fixed point package, as defined according to the VHDL 2008 standard. Hardware performance analysis results are presented in this paper for more than 75 circuit variations implemented on a Virtex-5 Xilinx FPGA, each for different parameter values of the proposed CORDIC module. A maximum 47% increase of speed, and 57% area reduction are accomplished, in comparison with other designs.