A delay minimization router: (TD)2 router

Since the interconnect delay has become the dominating factor in circuit performance, demands for a good delay-minimization router are very high. In this paper, we propose an algorithm to find a routing tree of a net which minimizes a total weighted delay τ to all sinks (input terminals), where the weight assigned to a sink represents a criticality of the delay to the sink. The algorithm uses top-down manner in determining the routing tree. Namely, the routing tree is determined from source (output terminal) to sinks. We also show experimental results to evaluate the performance of the proposed algorithm