Moore´s Law and Beyond: Electronic Design Challenges

CMOS integrated circuit technology is expected to scale down for a few more technology nodes, enabling several billion transistors on a single chip. New technologies are now being explored as potential successors to CMOS. This talk will explore the challenges in electronic design, both with the next generations of CMOS technology and with potential new replacements. The challenges include high-level and hierarchical design approaches with abstractions for the building blocks to deal with the increasing complexities and new technologies. Designs need to trade off between performance and power. New techniques need to be developed to deal with the complexity of design verification and the problems of testing for subtle defects after manufacture. Other challenges include the need to deal with analog and RF blocks in a system, as well as the need to potentially include mechanical, chemical and biological elements for sensors. Finally, the question needs to be raised whether we are making the best use of the computational elements we have.