Relaxed tree search MIMO signal detection algorithm design and VLSI implementation

Author

Chen, Sizhong ; Zhang, Tong ; Goel, Manish

Author_Institution

Dept. of Electr. Comput. & Sci. Eng., Rensselaer Polytech. Inst., Troy, NY

fYear

2006

fDate

21-24 May 2006

Lastpage

1150

Abstract

This paper presents an implementation-oriented breadth-first tree search MIMO detector design solution. Techniques at algorithm and VLSI architecture levels are developed to improve the implementation efficiency. Using Synopsys synthesis tool with 0.13 mum CMOS technology, we designed soft-output detectors for 4 times 4 MIMO channel with 64-QAM modulation. With the silicon areas less than 15 mm ², the detectors can achieve up to about 80 Mbps and realize the performance very close to detectors using the sphere decoding algorithm

Keywords

CMOS integrated circuits; MIMO systems; VLSI; quadrature amplitude modulation; signal detection; tree searching; 0.13 micron; 64-QAM modulation; CMOS technology; Synopsys synthesis tool; VLSI; breadth-first tree search MIMO detector design; relaxed tree search MIMO signal detection; sphere decoding algorithm; Algorithm design and analysis; CMOS technology; Decoding; Detectors; MIMO; Signal design; Signal detection; Signal synthesis; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692793

Filename

1692793