Multiple Bit Error Detection and Correction in GF Arithmetic Circuits

This paper presents a design technique for multiple bit error correctable (fault tolerant) polynomial basis (PB) multipliers over GF(2^m). These multipliers are the building blocks in certain types of cryptographic hardware, e.g. the Elliptic Curve Crypto systems (ECC). One of the drawbacks in the existing techniques is their inability to correct multiple bit errors at the outputs. Also, much attention has been given to error detection, as opposed to error correction. However, owing to possible security threats induced by soft or transient faults in cryptographic hardware, in certain cases multiple bit error correction, as a way of mitigating attacks, is more important than detection. To this end, we use multiple parity predictions to detect multiple errors based on popular error correcting codes. First, we present a multiple error detection scheme using Low Density Parity Check Codes (LDPC). The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. For multiple bit error correction we use Reed Solomon codes. Comparison with traditional techniques shows improved area and power performance.