DocumentCode
2534342
Title
A fast-locking digital delay line with duty-conservation
Author
Koh, Yun-Hak ; Kwon, Oh-Kyong
Author_Institution
Dept. of Electr. Eng., Hanyang Univ., Seoul, South Korea
fYear
1998
fDate
24-27 Nov 1998
Firstpage
287
Lastpage
290
Abstract
A two-clock-cycle locking and duty-conserving digital delay line is presented. The proposed delay line has a new matching detection circuit which can decide the tapping position within the detecting resolution range of 0.3 ns. The proposed delay line has duty-conserved 2-clock-cycle locking time at the frequency range of 70-180 MHz using 0.5 μm CMOS process
Keywords
CMOS digital integrated circuits; delay lines; timing; 0.5 micron; 70 to 180 MHz; CMOS process; duty-conservation; fast-locking digital delay line; matching detection circuit; tapping position; two-clock-cycle locking; CMOS process; Clocks; Delay effects; Delay lines; Driver circuits; Frequency; Microprocessors; Mirrors; Phase locked loops; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location
Chiangmai
Print_ISBN
0-7803-5146-0
Type
conf
DOI
10.1109/APCCAS.1998.743748
Filename
743748
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