Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range

Author

Akgun, Omer Can ; Leblebici, Yusuf

Author_Institution

Microelectron. Syst. Lab., Swiss Fed. Inst. of Technol., Lausanne

fYear

2006

fDate

21-24 May 2006

Abstract

In this paper the advantages of using differential cascode voltage switch pass gate (DCVSPG) logic with regard to standard CMOS for subthreshold operation are presented. The two families are compared in terms of their performance and energy-delay-product (EDP) figures. Multiple gates were simulated using 0.18 mum standard CMOS technology. Simulation results show that DCVSPG NAND2 gate has 71%, DCVSPG NOR2 gate has 82% and DCVSPG full adder has 66% EDP savings over the CMOS counterparts

Keywords

CMOS logic circuits; adders; circuit simulation; logic gates; 0.18 micron; CMOS logic circuit; DCVSPG NAND2 gate; DCVSPG NOR2 gate; DCVSPG full adder; DCVSPG logic circuit; EDP; differential cascode voltage switch pass gate; energy-delay-product; multiple gates; subthreshold operation; Adders; CMOS logic circuits; CMOS technology; Energy consumption; Frequency; Logic gates; MOSFETs; Microprocessors; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1692819

Filename

1692819

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2534566