DocumentCode
2536140
Title
Parallel processing addition and subtraction using binary coded redundant positive-digit number representation
Author
Tabata, Tom ; Ueno, Fumio ; Inoue, Takahiro
Author_Institution
Kumamoto Nat. Coll. of Technol., Japan
fYear
1998
fDate
24-27 Nov 1998
Firstpage
639
Lastpage
642
Abstract
The redundantly-represented positive-digit number addition is one of the most effective methods in producing digital addition circuits at higher speed. In this paper, a new voltage-mode multiple-radix parallel processing addition circuit using positive redundantly-expressed binary-coded numbers is discussed
Keywords
parallel processing; redundant number systems; binary coded redundant positive-digit number representation; digital arithmetic; positive redundantly-expressed binary-coded numbers; redundantly-represented positive-digit number addition; voltage-mode multiple-radix parallel processing circuit; Adders; Concurrent computing; Current mode circuits; Decoding; Delay effects; Digital arithmetic; Educational institutions; Parallel processing; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on
Conference_Location
Chiangmai
Print_ISBN
0-7803-5146-0
Type
conf
DOI
10.1109/APCCAS.1998.743901
Filename
743901
Link To Document