Modeling of SOI FET for RF switch applications

This paper presents the modeling of an SOI FET for RF switch applications. Given that the HF small-signal predictability, i.e. the insertion loss and the isolation, is a common state of the art, the study focuses on the modeling of the non-linearity of the FET. The non-linearity of an SOI FET switch arises from not just the transistor, but also the SOI substrate through various mechanisms. First the non-linearity is caused by the voltage imbalance, a direct result of the substrate loss, in a switch made of many FETs stacked in series. The voltage imbalance is the main non-linearity contributor to a FET switch at high-power levels. Secondly the substrate itself is non-linear and sets the harmonic floor. Besides the substrate, the impact of other important SOI physics, such as the floating-body effect and the parasitic BJT effect, to the switch linearity will also be discussed. Finally a hybrid model that combines PSP as the FET core and a layout-dependent non-linear SOI substrate model is presented, and excellent non-linearity predictability was demonstrated on a real-life RF switch.