SEU Hardened Flip-Flop Based on Dynamic Logic

A conventional master-slave flip-flop is very sensitive to particle strike that causes an SEU. When the clock is high, an SEU may upset the logic state of the master latch resulting in a faulty output of this flip-flop, and the erroneous value will also be locked in the slave latch when clock is low. When the clock is low, an SEU may also upset the logic state of the slave latch, resulting in a faulty output of this flip-flop. This paper presents an SEU hardened flip-flop that can mitigate SEU using an error detection circuit and a multiplexer. When the clock is high or low, an SEU in the master or slave latch of a flip-flop can be detected by the error detection circuit using dynamic logic. The multiplexer selects a correct output according to the error indication signal. The proposed flip-flop has small area, power and delay overheads and good radiation hardening capabilities.