A bidirectional linear semi-systolic architecture for DCT-domain image resizing processor

In recent times, there is an increasing interest in compressed-domain image analysis and its VLSI implementation due to extensive use multimedia communication, specially in mobile devices. This paper deals with the semi systolic architecture of DCT-based (discrete cosine transform) image resizing processor as a compressed domain image processing element. Further, we propose an efficient method for VLSI implementation for DCT-domain image resizing transformation with bidirectional linear semi-systolic array. This method is developed from the investigation of the DCT-domain image resizing operation through a parallel processing of the matrix operations. The use of systolic arrays as a processing block of the matrix operations reduces the number of computation and also amenable for VLSI implementation