Power efficient distributed low-noise amplifier in 90 nm CMOS

Author

Machiels, Brecht ; Reynaert, Patrick ; Steyaert, Michiel

Author_Institution

ESAT-MICAS, K.U. Leuven, Heverlee, Belgium

fYear

2010

fDate

23-25 May 2010

Firstpage

131

Lastpage

134

Abstract

A low-power wideband distributed low-noise amplifier (DLNA) in 90 nm CMOS is presented. Various techniques have been combined in the design to increase the distributed amplifier´s power efficiency. These techniques range from moderate inversion biasing to transmission line tapering. The measured gain of the 12.5 mW DLNA is larger than 15 dB from DC to 21 GHz. The average noise figure in the pass-band is 5.4 dB, the IIP3 at 5 GHz is -6.6 dBm and the total die area is 0.41 mm².

Keywords

CMOS integrated circuits; distributed amplifiers; low noise amplifiers; low-power electronics; wideband amplifiers; CMOS process; frequency 5 GHz; inversion biasing; low-power wideband distributed low-noise amplifier; noise figure 5.4 dB; power 12.5 mW; power efficiency; size 90 nm; transmission line tapering; Broadband amplifiers; Delay; Distributed amplifiers; Energy consumption; Impedance; Low-noise amplifiers; Power amplifiers; Power generation; Power transmission lines; Transmission line matrix methods; CMOS; broadband; distributed amplifier; low-noise amplifier (LNA); low-power; tapered;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE

Conference_Location

Anaheim, CA

ISSN

1529-2517

Print_ISBN

978-1-4244-6240-7

Type

conf

DOI

10.1109/RFIC.2010.5477322

Filename

5477322