• DocumentCode
    2540571
  • Title

    Exploiting basic block value locality with block reuse

  • Author

    Huang, Jian ; Lilja, David J.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Minnesota Univ., Minneapolis, MN, USA
  • fYear
    1999
  • fDate
    9-13 Jan 1999
  • Firstpage
    106
  • Lastpage
    114
  • Abstract
    Value prediction at the instruction level has been introduced to allow more aggressive speculation and reuse than previous techniques. We investigate the input and output values of basic blocks and find that these values can be quite regular and predictable, suggesting that using compiler support to extend value prediction and reuse to a coarser granularity may have substantial performance benefits. For the SPEC benchmark programs evaluated, 90% of the basic blocks have fewer than 4 register inputs, 5 live register outputs, 4 memory inputs and 2 memory outputs. About 16% to 41% of all the basic blocks are simply repeating earlier calculations when the programs are compiled with the -O2 optimization level in the GCC compiler. We evaluate the potential benefit of basic block reuse using a novel mechanism called a block history buffer. This mechanism records input and live output values of basic blocks to provide value prediction and reuse at the basic block level. Simulation results show that using a reasonably sized block history buffer to provide basic block reuse in a 4-way issue superscalar processor can improve execution time for the tested SPEC programs by 1% to 14% with an overall average of 9%
  • Keywords
    buffer storage; instruction sets; parallel architectures; parallel programming; program compilers; software reusability; storage allocation; -O2 optimization level; 4-way issue superscalar processor; GCC compiler; SPEC benchmark programs; SPEC programs; aggressive speculation; basic block reuse; basic block value locality; block history buffer; block reuse; coarser granularity; compiler support; execution time; instruction level; live register outputs; memory inputs; memory outputs; performance benefits; register inputs; value prediction; Accuracy; Computer aided instruction; Computer science; Ear; History; Optimizing compilers; Program processors; Registers; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 1999. Proceedings. Fifth International Symposium On
  • Conference_Location
    Orlando, FL
  • Print_ISBN
    0-7695-0004-8
  • Type

    conf

  • DOI
    10.1109/HPCA.1999.744342
  • Filename
    744342