DocumentCode
2541194
Title
Linear pocket profile based threshold voltage model for Sub-100 nm n-MOSFET incorporating substrate and drain bias effects
Author
Bhuyan, Muhibul Haque ; Khosru, Quazi D M
Author_Institution
Dept. of Electron. & Telecommun. Eng., Daffodil Int. Univ., Dhaka
fYear
2008
fDate
20-22 Dec. 2008
Firstpage
447
Lastpage
451
Abstract
This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poissonpsilas equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The result is compared with two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Keywords
MOSFET; semiconductor device models; ULSI; drain bias effect; gate lengths; linear equations; linear pocket profiles; n-MOSFET; substrate bias effect; threshold voltage model; Circuit simulation; Doping profiles; Electronic mail; MOSFET circuits; Poisson equations; Semiconductor process modeling; Surface fitting; Telecommunication computing; Threshold voltage; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 2008. ICECE 2008. International Conference on
Conference_Location
Dhaka
Print_ISBN
978-1-4244-2014-8
Electronic_ISBN
978-1-4244-2015-5
Type
conf
DOI
10.1109/ICECE.2008.4769249
Filename
4769249
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