DocumentCode
2541561
Title
Efficient deblocking filter architecture for H.264 video coders
Author
Lin, Heng-Yao ; Yang, Jwu-Jin ; Liu, Bin-Da ; Yang, Jar-Ferr
Author_Institution
Dept. of Electr. Eng., National Cheng Kung Univ., Tainan
fYear
2006
fDate
21-24 May 2006
Abstract
In this paper, an efficient in-loop deblocking filter architecture for H.264 video coding system is proposed. The deblocking filter usually need perform both vertical and horizontal directions. A novel data arrangement, called the group-of-pixel (GOP), is designed to efficiently arrange the pixel data stored in on-chip memory. With the proposed GOP arrangement, we do not need the transpose memory, which often occupies excessive chip area, to transpose the direction of the pixel data filtering. Furthermore, the number of total cycles required for GOP-based deblocking filter is reduced significantly. The proposed in-loop GOP-based deblocking filter architecture synthesized with UMC 0.18 mum technology could process real-time video in 720p HD (1280times720) format operated at 100 MHz
Keywords
adaptive filters; video coding; 0.18 micron; 100 MHz; GOP arrangement; H.264 video coders; H.264 video coding system; UMC technology; data arrangement; deblocking filter architecture; group-of-pixel arrangement; on-chip memory; pixel data filtering; Acceleration; Adaptive filters; Automatic voltage control; Decoding; Filtering; Hardware; Low pass filters; Quantization; Random access memory; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693160
Filename
1693160
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