A scalable novel P-channel nonvolatile memory cell

Scalability and reliability of a split-gate, p-channel flash E²PROM cell (Caywood et al., 2000) which uses channel FN tunneling for program/erase operations have been investigated. Evaluations of the cell after 10⁶ cycles by charge-pumping (CP) and stress induced leakage current (SILC) methods have also been performed. The cell features merged select transistors (MST) in series with a floating-gate transistor. By utilizing an oxide-nitride-oxide (ONO) stack as both gate dielectric of MST and inter-poly dielectric (IPD) film between floating gate (FG) and control gate (CG) of cell, the performance and scalability are improved considerably. The feasibility of scaling down this memory cell into the 0.18mum generation is demonstrated