Proposed DPWM Scheme with Improved Resolution for Switching Power Converters

Because of the need to eliminate the limit-cycle oscillations, a high-resolution DPWM scheme is mandatory, especially for the applications with high switching frequency and tight output regulation. Therefore, the dual-clock DPWM scheme is proposed in this paper. With two relative low frequency clocks, a much higher equivalent frequency is achieved for the DPWM; hence, the DPWM resolution is increased. With the proposed scheme, it is possible to implement the DPWM without delay lines even for high-frequency converters, which reduces the cost for the digital controller significantly. Experiment results based on a 300-kHz buck converter verify the improvement.