Parasitic resistance reduction technology

Author

Ok, I. ; Loh, W.-Y. ; Ang, K.-W. ; Young, C.D. ; Hung, P.Y. ; Ngai, T. ; Akarvardar, K. ; Hobbs, C. ; Jammy, R.

Author_Institution

SEMATECH, Albany, NY, USA

fYear

2011

fDate

9-10 June 2011

Firstpage

50

Lastpage

54

Abstract

We reported double-gate transistors with reduced source-drain (SD) resistance with aluminum (Al) implant on S/D for sub 22 nm technology node. Al implanted S/D can provide to modulate the electron barrier height of PtSi towards the conduction band. We also investigate Schottky barrier modulation using a new Ge ion implantation (I/I) and segregation approach and the impact of spike anneal on the SBH tuning. Novel silcide alloys of Ni with Yb or Er can be adopted for a FinFET structure. These techniques attribute constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.

Keywords

MOSFET; Schottky barriers; aluminium compounds; annealing; conduction bands; germanium compounds; ion implantation; segregation; FinFET structure; PtSi; SBH tuning; SD resistance; Schottky barrier modulation; aluminum implant; conduction band; double-gate transistors; electron barrier height; enhanced drive current; germanium ion implantation; high performance technology nodes; nonplanar cMOS integration sequence; parasitic resistance reduction technology; reduced source-drain resistance; segregation approach; silcide alloys; size 2 nm; spike anneal; Annealing; Implants; Jamming; Lead;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology (IWJT), 2011 11th International Workshop on

Conference_Location

Kyoto

Print_ISBN

978-1-61284-131-1

Type

conf

DOI

10.1109/IWJT.2011.5969998

Filename

5969998