A fast implementation of modular inversion over GF (2m) based on FPGA

Author

Dong-Mei, Wei

Author_Institution

Sch. of Inf. Eng., Univ. of SWUST, Mianyang, China

fYear

2010

fDate

16-18 April 2010

Firstpage

465

Lastpage

468

Abstract

A fast algorithm for modular inversion over GF(2m) using Fermat´s Little Theorem is presented. A parallel modular multiplication algorithm and a cascade modular square block to reduce the times of modular exponentiation are given. Synthesis and implementation are realized in a Xilinx device of XC5VLX110T. By timing simulation, the clock frequency can achieve 50MHz. It is required to carry out one modular inversion operation in 0.5μs with 25 clock periods.

Keywords

Galois fields; field programmable gate arrays; public key cryptography; timing; FPGA; GF (2m); XC5VLX110T; Xilinx device; cascade modular square block; frequency 50 MHz; modular inversion; parallel modular multiplication algorithm; time 0.5 mus; timing simulation; Clocks; Digital signatures; Elliptic curve cryptography; Field programmable gate arrays; Frequency synthesizers; Hamming weight; Parallel algorithms; Polynomials; Public key cryptography; Timing; FLT; FPGA; keywords-modular inversion; parallel modular multiplication algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Management and Engineering (ICIME), 2010 The 2nd IEEE International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-5263-7

Electronic_ISBN

978-1-4244-5265-1

Type

conf

DOI

10.1109/ICIME.2010.5477629

Filename

5477629