A novel ternary more, less and equality circuit using recharged semi-floating gate devices

Author

Gundersen, Henning ; Berg, Yngvar

Author_Institution

Microelectron. Syst. Group, Oslo Univ.

fYear

2006

fDate

21-24 May 2006

Lastpage

3172

Abstract

This paper presents a novel ternary more, less and equality (MLE) circuit implemented with recharged semi-floating gate transistors. The circuit is a ternary application, and ternary structures may offer the fastest search in a tree structure. The circuit has two ternary inputs, and one ternary output which will be a comparison of the two ternary inputs. The circuit is a useful building block for use in a search tree application. The circuit is simulated by using Cadencereg Analog Design Environment with CMOS090 GP process parameters from STMicroelectronics, a 90 nm general purpose bulk CMOS process with 7 metal layers. The circuit operates at a 1 GHz clock frequency. The supply voltage is plusmn0.5 Volt. All capacitors are metal plate capacitors, based on a vertical coupling capacitance between stacked metal plates

Keywords

CMOS logic circuits; capacitors; logic design; logic gates; ternary logic; 1 GHz; 90 nm; Cadence Analog Design Environment; MLE circuit; bulk CMOS process; metal plate capacitors; recharged semifloating gate devices; search tree application; semifloating gate transistors; ternary more less and equality circuit; ternary structures; tree structure; vertical coupling capacitance; CMOS process; Capacitance; Capacitors; Circuit simulation; Clocks; Coupling circuits; Frequency; Maximum likelihood estimation; Tree data structures; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693298

Filename

1693298