A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process

An adaptive bandwidth phase-locked loop (PLL) uses a switched-capacitor equivalent resistor circuit in the loop filter and a multistage inverse-linear programmable current mirror to bias of the charge pump for not only the proper loop bandwidth but also constant phase margin and are independent of multiplication factor, reference frequency, output frequency, process, voltage and temperature. The charge pump with op amp is used to reduce leakage current in the nano-scale process, when the PLL can require large multiplication range for proper jitter performance. The HSPICE simulation results are based on UMC 0.09-mum Ip9m CMOS process and the supply voltage is 1V. The simulation results show the proposed PLL can achieve a reference frequency range of 0.977-50MHz, a multiplication range of 1-1023 with output frequency range of 100MHz-1GHz. When the output frequency is 1GHz, the power dissipation is 3.252mW