A 20.5GHz wide-band programmable divide-by-N frequency divider

Author

Guo Ting ; Zhiqun Li ; Qin Li ; Zhigong Wang

Author_Institution

Sch. of Integrated Circuits, Southeast Univ., Nanjing, China

fYear

2014

fDate

10-12 Dec. 2014

Firstpage

164

Lastpage

167

Abstract

A 1.2V wide-band programmable divide-by-N frequency divider (FD) with consecutive 16-519 division ratios has been designed and fabricated using standard 90nm CMOS technology. The programmable FD consists of a high speed divide-by-8/9 dual-modulus prescaler, a pulse counter (P counter) and a swallow counter (S counter). Dynamic current-mode logic (DCML) DFF and signal locking technique have been used in this divider to achieve high speed operation. The proposed divider exhibits wide frequency range from 7GHz to 20.5GHz and dissipates 8.52mW power consumption at 1.2V voltage supply. Utilizing this FD, a charge-pump based PLL has been realized with 31.5GHz-34GHz frequency range. The phase noise of the PLL at 34.027GHz is -91.3dBc/Hz@1MHz offset. This PLL consumes 30.72mW power and occupies 1.32mm×1.01mm chip area.

Keywords

CMOS integrated circuits; current-mode logic; field effect MIMIC; field effect MMIC; frequency synthesizers; integrated circuit design; phase noise; CMOS technology; DCML DFF; FD; charge-pump based PLL; dynamic current-mode logic; frequency 7 GHz to 34.027 GHz; high speed divide-by-8/9 dual-modulus prescaler; phase noise; power 30.72 mW; power 8.52 mW; pulse counter; signal locking technique; size 90 nm; swallow counter; voltage 1.2 V; wide-band programmable divide-by-N frequency divider; CMOS integrated circuits; Flip-flops; Frequency conversion; Phase locked loops; Phase noise; Power demand; Radiation detectors; CMOS; divide-by-N; frequency divider; pulse/swallow counter; wide-band;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits (ISIC), 2014 14th International Symposium on

Conference_Location

Singapore

Type

conf

DOI

10.1109/ISICIR.2014.7029472

Filename

7029472