A 10-/spl mu/W digital signal processor with adaptive-SNR monitoring for a sub-1V digital hearing aid

Author

Yoo, Jerald ; Kim, Sunyoung ; Cho, Namjun ; Song, Seong-Jun ; Yoo, Hoi-Jun

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon

fYear

2006

fDate

21-24 May 2006

Abstract

An ultra low-power digital signal processor (DSP) is proposed for the digital hearing aid. The DSP has a SNR monitor to vary its internal clock frequency in accordance with the input signal level. Digital filters use hardwired barrel shifters in place of multipliers, and a parameter ROM provides filter parameters. The clock generator consumes only 1 muW at sub-1V. The DSP consumes only 10 muW at 0.9-V single supply, and occupies 0.3 mm² with gate count of 10k using 0.18-mum CMOS process

Keywords

CMOS digital integrated circuits; clocks; digital filters; digital signal processing chips; hearing aids; low-power electronics; read-only storage; 0.18 micron; 0.9 V; 1 V; 1 muW; 10 muW; CMOS process; adaptive-SNR monitoring; barrel shifters; clock generator; digital filters; digital hearing aid; digital signal processor; filter parameters; parameter ROM; Auditory system; Clocks; Digital filters; Digital signal processing; Digital signal processors; Energy consumption; Frequency; Monitoring; Read only memory; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693346

Filename

1693346