DocumentCode
2545170
Title
On-Chip Bus Design for HDTV SoC Decoder
Author
Yi Zhiqiang ; Li Yun
Author_Institution
Coll. of Telecommun. Eng., Hangzhou Dianzi Univ., Hangzhou, China
fYear
2010
fDate
23-25 Sept. 2010
Firstpage
1
Lastpage
3
Abstract
It is a great challenge to design an On-Chip Bus (OCB) system to meet the extremely high bandwidth requirements in HDTV SoC decoder. In this paper, an OCB system with high throughput and flexibility based on the multi-bus architecture is proposed. A bus switch with multi-level arbiter structure is also constructed thereafter. Simulation results show that the OCB system can ensure the real-time performance of the whole decoder very well.
Keywords
codecs; high definition television; system buses; system-on-chip; HDTV SoC decoder; multilevel arbiter structure; on-chip bus design; Bandwidth; Data communication; Decoding; HDTV; Media; Streaming media; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communications Networking and Mobile Computing (WiCOM), 2010 6th International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-3708-5
Electronic_ISBN
978-1-4244-3709-2
Type
conf
DOI
10.1109/WICOM.2010.5600131
Filename
5600131
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