• DocumentCode
    2546693
  • Title

    Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes

  • Author

    Zhang, Zhuo ; Reddy, Sudhakar M. ; Pomeranz, Irith

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA
  • fYear
    2007
  • fDate
    23-26 Jan. 2007
  • Firstpage
    817
  • Lastpage
    822
  • Abstract
    Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift test method has the advantage that it provides higher fault coverage at reduced test generation time and test pattern counts. However a concern expressed often in the literature is the potential over testing or yield loss caused by the fact that launch off shift operates the circuit under test in non-functional manner. In this paper we present data, for the first time, which points to another potential problem with launch off shift tests. The data presented for ISCAS-89 benchmark circuits shows that a considerable numbers of functionally detectable transition delay faults are not detected by the normally used launch off shift tests that use a single fault activation cycle. Functionally detectable faults that escape tests could cause circuit malfunction in normal operation. Thus launch off shift tests when used in manufacturing test may result in test escapes. We also present data that shows that if launch off shift tests with multiple fault activation cycles are used essentially all functionally detectable faults can be detected.
  • Keywords
    automatic test pattern generation; fault diagnosis; integrated circuit testing; ISCAS-89 benchmark circuits; circuit under test; detect delay faults test; fault coverage; launch off capture test; launch off shift test; scan designs; single fault activation cycle; test generation time; test pattern counts; transition delay faults; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Delay; Electrical fault detection; Fault detection; Lab-on-a-chip; Manufacturing; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    1-4244-0629-3
  • Electronic_ISBN
    1-4244-0630-7
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2007.358090
  • Filename
    4196136