DocumentCode
2547353
Title
A 3.5Gbit/s post-amplifier in 0.18μm CMOS
Author
Hermans, Carolien ; Steyaert, Michiel
Author_Institution
ESAT-MICAS, K.U. Leuven, Belgium
fYear
2005
fDate
12-16 Sept. 2005
Firstpage
431
Lastpage
434
Abstract
A postamplifier with output buffer implemented in a standard 0.18μm 1.8V CMOS technology is proposed. Using broadband techniques for both postamplifier and output buffer, highspeed operation has been achieved. For a differential 10mVpp 231-1 pseudo random bit sequence, a bit error rate of 5·10-12 at 3.5Gbit/s has been measured. At lower bitrates the bit error rate is even lower: a 1 Gbit/s 10mVpp, input signal results in a bit error rate of 7·10-14. The rms jitter is 12ps. The postamplifier circuit consumes only 19mA from a 1.8V power supply.
Keywords
CMOS integrated circuits; amplifiers; buffer circuits; integrated circuit design; integrated circuit noise; 0.18 micron; 1.8 V; 12 ps; 19 mA; 3.5 Gbit/s; CMOS technology; broadband techniques; postamplifier circuit; pseudo random bit sequence; rms jitter; Bandwidth; Circuits; Degradation; Differential amplifiers; Frequency response; Output feedback; Performance gain; Radiofrequency amplifiers; Resistors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN
0-7803-9205-1
Type
conf
DOI
10.1109/ESSCIR.2005.1541652
Filename
1541652
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