• DocumentCode
    2548067
  • Title

    Process-insensitive modulated-clock voltage comparator

  • Author

    Taillefer, Christopher S. ; Roberts, Gordon W.

  • Author_Institution
    McGill Univ., Montreal, Que.
  • fYear
    2006
  • fDate
    21-24 May 2006
  • Abstract
    A comparator design methodology is proposed that is digitally calibrated for process variability and digitally-synthesizable. The proposed comparator design was fabricated in a 0.18-mum CMOS process. Experimental results demonstrate that the comparator does compensate for process variation, with an 8-bit resolution while operating at a sampling rate of 25 MHz
  • Keywords
    CMOS integrated circuits; calibration; comparators (circuits); 0.18 micron; 25 MHz; CMOS process; comparator design; digital calibration; modulated-clock voltage comparator; process variation; CMOS process; CMOS technology; Calibration; Clocks; Delay; Flip-flops; Logic; Virtual colonoscopy; Virtual reality; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
  • Conference_Location
    Island of Kos
  • Print_ISBN
    0-7803-9389-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2006.1693483
  • Filename
    1693483
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2548067