Joint and marginal probability analyses of Markov Random Field networks for digital logic circuits

With the device scaling up to nano-level, the integrated circuits are expected to face high computing error rates. This increased rate is the outcome of random and dynamic noise injected in the circuit which becomes more vulnerable due to low supply voltages and extremely small transistor dimensions. Markov Random Field (MRF) modelling is one approach to achieve noise-tolerance in integrated circuit design. As a general overview of fault-tolerance, we start with comparing on-going techniques for fault-tolerant design. Later, we explain the two basic terminologies of MRF i.e. Joint and Marginal Probability followed by their computation for M3 module of C432 Interrupt Controller (as our test circuit). The contribution of this paper is the derivation of circuit design rules based on the conclusions obtained by these two probability analyses.