• DocumentCode
    2551862
  • Title

    A comparative study of pseudo stuck-at and leakage fault model

  • Author

    Zachariah, Sujit Thomas ; Chakravarty, Sreejit

  • Author_Institution
    Dept. of Comput. Sci. & Eng., State Univ. of New York, Buffalo, NY, USA
  • fYear
    1999
  • fDate
    7-10 Jan 1999
  • Firstpage
    91
  • Lastpage
    94
  • Abstract
    Pseudo stuck-at is a popular model, used by many commercial tool vendors, for evaluating and selecting IDDQ tests. We show that pseudo stuck-at fault coverage numbers are very pessimistic, and equally good vectors can be selected much faster using the leakage fault model. This, and the fact that a fast simulation algorithm exists for leakage faults, prompts us to propose the use of the leakage fault model
  • Keywords
    fault simulation; integrated circuit modelling; integrated circuit testing; IDDQ testing; leakage fault model; pseudo stuck-at fault model; simulation algorithm; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Computer science; Current measurement; Current supplies; Insulation; Manufacturing; Steady-state;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1999. Proceedings. Twelfth International Conference On
  • Conference_Location
    Goa
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-0013-7
  • Type

    conf

  • DOI
    10.1109/ICVD.1999.745130
  • Filename
    745130
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2551862