MPEG-2 video data simulator: a case study in constrained HW-SW codesign

Author

Goswami, Rashmi ; Srinivasan, V. ; Balakrishnan, M.

Author_Institution

Cadence Design Syst., Noida, India

fYear

1999

fDate

7-10 Jan 1999

Firstpage

128

Lastpage

131

Abstract

An MPEG-2 video data simulator has been designed in a constrained design space. A hierarchical FSM model has been developed for MPEG-2 video data simulator. This model can be used for any sequence of moving pictures. This model was verified by behavioral (C-language) simulation for a particular case (color-bars data and I I I picture sequence). After an evaluation of the implementation options available in our fairly constrained design space, firmware implementation was selected and implemented

Keywords

C language; data compression; digital simulation; finite state machines; firmware; hardware-software codesign; signal generators; telecommunication standards; video coding; C-language simulation; I I I picture sequence; MPEG-2 video; behavioral simulation; color-bars data; constrained HW-SW codesign; constrained design space; firmware implementation; hierarchical FSM model; implementation options; moving picture sequence; video data simulator; Computer aided software engineering; Counting circuits; Data mining; Decoding; Hardware; Microcontrollers; Streaming media; Switches; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Conference_Location

Goa

ISSN

1063-9667

Print_ISBN

0-7695-0013-7

Type

conf

DOI

10.1109/ICVD.1999.745136

Filename

745136