A novel match-line selective charging scheme for high-speed, low-power and noise-tolerant content-addressable memory

Author

Hasan, M.M. ; Rashid, A.B.M.H. ; Hussain, M.M.

Author_Institution

Dept. of Electr. Eng., King Abdullah Univ. of Sci. & Technol. (KAUST), Thuwal, Saudi Arabia

fYear

2010

fDate

15-17 June 2010

Firstpage

1

Lastpage

4

Abstract

Content-addressable memory (CAM) is an essential component for high-speed lookup intensive applications. This paper presents a match-line selective charging technique to increase speed and reduce the energy per bit per search while increasing the noise-tolerance. Simulation in TSMC 0.18 μm technology with 64×72 Ternary CAM shows the match-line energy reduction of 45% compared to the conventional current-saving scheme with the reduction of minimum cycle time by 68% and the improvement of noise-tolerance by 96%.

Keywords

CMOS memory circuits; content-addressable storage; high-speed integrated circuits; low-power electronics; TSMC technology; high-speed content-addressable memory; high-speed lookup intensive applications; low-power content-addressable memory; match-line selective charging scheme; noise-tolerant content-addressable memory; size 0.18 mum; ternary content-addressable memory; Arrays; Computer aided manufacturing; Noise; Power demand; Sensors; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent and Advanced Systems (ICIAS), 2010 International Conference on

Conference_Location

Kuala Lumpur, Malaysia

Print_ISBN

978-1-4244-6623-8

Type

conf

DOI

10.1109/ICIAS.2010.5716226

Filename

5716226