Design and simulation difference types CMOS phase frequency detector for high speed and low jitter PLL

Author

Arshak, K. ; Abubaker, O. ; Jafer, E.

Author_Institution

Dept. of Electron. & Comput. Eng., Limerick Univ., Ireland

Volume

1

fYear

2004

fDate

3-5 Nov. 2004

Firstpage

188

Lastpage

191

Abstract

This paper presents the different design schemes of the phase frequency detector (PFD) and compares the output simulation results. The circuits that have been considered are the standard CMOS (S_PFD), true single-phase clock PFD (TSPC_PFD), DCVSL differential cascode voltage switch logic PFD (DCVSL_PFD) and current mode logic PFD (CML_PFD). The simulation results are focused on exploring the dead zone, high frequency operation, power dissipation and phase noise of the different PFD. The results reported in this paper based on simulation done using SpectreS extracted layout. The different circuits of PFD are designed using 0.35 μm CMOS technology with 3.3V supply voltage.

Keywords

CMOS analogue integrated circuits; circuit simulation; current-mode circuits; integrated circuit design; logic circuits; phase detectors; phase locked loops; 0.35 micron; 3.3 V; CML_PFD; CMOS analog integrated circuits; CMOS phase frequency detector; DCVSL differential cascode voltage switch logic PFD; DCVSL_PFD; TSPC_PFD; circuit simulation; current mode logic PFD; high speed PLL; integrated circuit design; low jitter PLL; phase locked loops; true single-phase clock PFD; CMOS logic circuits; CMOS technology; Circuit simulation; Clocks; Jitter; Phase frequency detector; Phase locked loops; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on

Print_ISBN

0-7803-8777-5

Type

conf

DOI

10.1109/ICCDCS.2004.1393380

Filename

1393380