Parameterizable implementation of full search block matching algorithm using FPGA for real-time applications

In this paper, a systolic array architecture for FSBMA is implemented by RTL-level VHDL for using as a motion estimation unit in low bit rate and real-time applications such as video telephony. This implementation is synthesized for two FPGA families, Xilinx Spartan II and Xilinx Virtex II and the results for area occupation and maximum opening frequency are presented. The results show it is possible to implement real-time video encoding systems with motion estimation, on a single FPGA chip.