Design and Implementation of Bandwidth Adaptable Third-Order All Digital Phase-Locked Loops

A bandwidth adaptable third-order all-digital phase-locked loop (PLL) based on PI control algorithm is proposed in this paper. On the analysis of the mathematical model of analog PLL system, mathematical model for bandwidth adaptable all-digital PLL is firstly established and theoretical analysis is therefore carried out, and then the relationship between the proportional/integral parameters of the PLL and the input signal frequency is derived. And finally under the Matlab/Simulink^® environment, system-level model for the PLL is directly constructed using DSP Builder^®, and system design is completed by using VHDL and is implemented on a FPGA based platform. Both system simulation and experimental results confirm the correctness of the design. The control parameters of this PLL change adaptively with the variation of input signal frequency, and it features with its high frequency-locking speed, wide frequency-tracking range, easy integration and broad versatility.