Systematic approach to ultra-wideband Low Noise Amplifier design in CMOS technology

Author

Roodaki, Parisa Momen ; Kondori, Maryam Baghban ; Amiri, Parviz

Author_Institution

Dept. of Electr. & Comput. Eng., Shariaty Univ., Tehran

fYear

2008

fDate

25-27 Nov. 2008

Firstpage

49

Lastpage

53

Abstract

A systematic approach to CMOS low noise amplifier design is presented. This Method uses a new input impedance matching technique based on LC Ladder Matching Networks. With This approach a LNA is implemented in ADS2006. Simulations results for 0.13 mum TSMC technology shows a very low noise figure less than 1.75 dB and power gain up to 20 dB in middle frequency. S11 and S22 are less than -7 dB and -10 dB in average respectively. This amplifier consumes only 8.846 mw power with 1 v supply voltage.

Keywords

CMOS analogue integrated circuits; impedance matching; integrated circuit design; low noise amplifiers; ultra wideband technology; ADS2006; CMOS low noise amplifier design; CMOS technology; LC ladder matching networks; impedance matching; power 8.846 mW; size 0.13 mum; ultra-wideband low noise amplifier design; voltage 1 V; CMOS technology; Low-noise amplifiers; Ultra wideband technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on

Conference_Location

Johor Bahru

Print_ISBN

978-1-4244-3873-0

Electronic_ISBN

978-1-4244-2561-7

Type

conf

DOI

10.1109/SMELEC.2008.4770275

Filename

4770275