DocumentCode
2553617
Title
Empirical computation of reject ratio in VLSI testing
Author
Mehta, Shashank K. ; Seth, Sharad C.
Author_Institution
Dept. of Comput. Sci. & Eng., Nebraska Univ., Lincoln, NE, USA
fYear
1999
fDate
7-10 Jan 1999
Firstpage
506
Lastpage
511
Abstract
Among significant components of testing cost are test-length, reject ratio, and lost-yield. In this paper a new approach is proposed to estimate the reject ratio. The empirical model is based on test-data properties that are believed to be invariant for a wide range of manufacturing technologies and types of tests. The analysis is carried out entirely in terms of the device test data, as might be available from a wafer probe. Experimental results demonstrate the robustness of the model
Keywords
VLSI; integrated circuit testing; probability; production testing; VLSI testing; empirical model; reject ratio computation; test-data properties; Automatic testing; Circuit faults; Circuit testing; Costs; Delay; Electrical capacitance tomography; Parameter estimation; Semiconductor device manufacture; Very large scale integration; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location
Goa
ISSN
1063-9667
Print_ISBN
0-7695-0013-7
Type
conf
DOI
10.1109/ICVD.1999.745205
Filename
745205
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