A semi-digital delay locked loop for clock skew minimization

Author

Park, Joonbae ; Koo, Yido ; Kim, Wonchan

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ., South Korea

fYear

1999

fDate

7-10 Jan 1999

Firstpage

584

Lastpage

588

Abstract

A two-step approach for fast locking of a DLL (delay-locked-loop) circuit is discussed. The locking process consists of two steps; the coarse tuning in digital domain by tapping a delay position for fast coarse locking, and the accurate phase synchronization between the external clock and the internal clock in analog operation mode. With this two step approach, fast locking and low phase error can be simultaneously achieved

Keywords

circuit tuning; clocks; delay lock loops; jitter; synchronisation; DLL; analog operation mode; clock skew minimization; coarse tuning; delay position; external clock; internal clock; locking process; phase synchronization; semi-digital delay locked loop; two-step approach; Bandwidth; Birth disorders; Circuit optimization; Clocks; Crosstalk; Delay lines; Filters; Jitter; Minimization; Phase detection;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Conference_Location

Goa

ISSN

1063-9667

Print_ISBN

0-7695-0013-7

Type

conf

DOI

10.1109/ICVD.1999.745218

Filename

745218

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2553835