Embedded Software Validation: Applying Formal Techniques for Coverage and Test Generation

The validation of embedded software in VLSI designs is becoming increasingly important with their growing prevalence and complexity. In this paper we present a new, hybrid, automated, validation methodology combining formal techniques and simulation. We introduce compositional approach to generate a formal model of the design, and show how the list of its feasible paths can be extracted. This list is then used for coverage metrics, and for test generation. This method has been successfully applied to complex microcode of a state-of-the-art microprocessor, and it is applicable to other classes of embedded software. Its effectiveness and scalability was demonstrated on a set of complex IA32 instructions, where unknown bugs have been detected and validation convergence time was reduced from weeks in a previous project to a matter of days.