Design and Simulation of an Optimized DDS

Author

Wang, Qing ; He, Songbai ; Zhong, Ziming

Author_Institution

Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China

fYear

2010

fDate

23-25 Sept. 2010

Firstpage

1

Lastpage

3

Abstract

In this paper, an improved design of direct digital synthesizer (DDS) based on the traditional frequency synthesizer theory is put forward. To achieve 32-bit DDS design, FPGA Statix II series chip are used. Besides, it has proposed 1/4 look-up table compression, phase jitter injection and other optimization methods. Moreover, error sources of the DDS spectrum spurious output is analyzed. Experimental results show that the improved DDS can generate sine wave with high precision, meanwhile the spurious free dynamic range can achieve 93 dB, which improves nearly 10 dB compared with that of unimproved DDS.

Keywords

direct digital synthesis; field programmable gate arrays; frequency synthesizers; table lookup; FPGA Statix II series chip; direct digital synthesizer; frequency synthesizer theory; look-up table compression; phase jitter injection; word length 32 bit; Clocks; Field programmable gate arrays; Frequency synthesizers; Jitter; Read only memory; Registers; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications Networking and Mobile Computing (WiCOM), 2010 6th International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-3708-5

Electronic_ISBN

978-1-4244-3709-2

Type

conf

DOI

10.1109/WICOM.2010.5600723

Filename

5600723