Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis

With aggressive technology scaling, gate oxide tunneling current is emerging as a prominent component of power dissipation in nanoCMOS circuits. This paper presents a novel approach for reduction of tunneling current (gate leakage) during behavioral synthesis using simultaneous scheduling and binding of resources made of transistors of different gate oxide thicknesses. We provide a heuristic algorithm for optimizing allocation and utilization of resources while scheduling operations with the objective of reducing gate leakage. We selectively bind the off-critical operations to instances of functional units that have transistors of higher oxide thickness, and critical operations to the functional units of lower oxide thickness. We performed extensive experiments for several behavioral synthesis benchmarks using a 45nm technology library. For a time constrained approach we achieved a maximum reduction of 84.8%, while for a resource-time constrained approach the reduction is 75.8%