• DocumentCode
    2557367
  • Title

    A novel technique integrating buffer insertion into timing driven placement

  • Author

    Luo, Lijuan ; Zhou, Qiang ; Cai, Yici ; Hong, Xianlong ; Wang, Yibo

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
  • fYear
    2006
  • fDate
    21-24 May 2006
  • Abstract
    Increasing buffer number for future technology makes traditional one-pass-flow (timing driven placement is followed by buffer insertion and legalization) failed, since accommodation for buffers significantly disturbs original design. This paper exploits the delicate relationship between buffer insertion and timing driven placement, and proposes a novel method to incorporate buffer insertion during timing driven placement. Experimental results show that this incorporation not only ensures design convergence, but also benefits timing behavior and alleviates buffer explosion
  • Keywords
    buffer circuits; circuit layout; graph theory; timing; buffer insertion; timing driven placement; Computer science; Convergence; Delay estimation; Design optimization; Explosions; Flip-flops; Integrated circuit interconnections; Space technology; Timing; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
  • Conference_Location
    Island of Kos
  • Print_ISBN
    0-7803-9389-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2006.1693904
  • Filename
    1693904