A 0.13 /spl mu/m CMOS delay cell for 40 Gb/s FFE equalization

This paper describes the design of a 1.2V delay cell for a 40 Gb/s fractionally spaced feedforward equalizer (FFE), simulated in 0.13 mum CMOS. The delay cell is based on a triple-resonance amplifier (TRA) architecture (Galal and Razavi, 2004), and incorporates varactors for a 4.7% delay tuning range. The circuit achieves a nominal delay of 8.33 ps (T/3 spacing) with a 7.2% delay variation up to 20 GHz. By using stacked inductors, a cell size of 42 mum times 39 mum was achieved. Each delay cell consumes 6mA of current, and has a post-layout extracted bandwidth of 40.6 GHz