First Pass MM-Wave Circuit Design in 65nm Digital CMOS

Author

Lee, Fred S. ; Aryanfar, Farshid ; Werner, Carl W.

Author_Institution

Rambus Inc., Los Altos, CA

fYear

2009

fDate

19-21 Jan. 2009

Firstpage

1

Lastpage

4

Abstract

A 60 GHz gain block is designed in a 65 nm digital CMOS 1P9M process using only digital CMOS models and a reduced metallization stack-up height to support redistribution layer routing for flip-chip designs. The design methodology utilizes current density, distributed, and lumped modeling to predict the measured center frequency of the gain block less than 1% from the simulated values. At 1 V and 5.3 mA, measured S₁₂, Sn, S₁₁, S₂₂, NF, and IP_1dB are 3dB, <-20dB, <-10dB, <-15 dB, 7.7 dB and -6 dBm respectively, across 57-64 GHz. Measurements at 2 V are also presented.

Keywords

CMOS digital integrated circuits; MIMIC; current density; flip-chip devices; integrated circuit design; integrated circuit metallisation; integrated circuit modelling; integrated circuit packaging; 60 GHz gain block; 65 nm digital CMOS; CMOS 1P9M process; current 5.3 mA; current density; digital CMOS model; distributed modeling; first pass mm-wave circuit design; flip-chip design; frequency 57 GHz to 64 GHz; lumped modeling; metallization stack-up height; redistribution layer routing; voltage 1 V; voltage 2 V; CMOS digital integrated circuits; CMOS process; Circuit synthesis; Current density; Density measurement; Design methodology; Metallization; Predictive models; Routing; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09. IEEE Topical Meeting on

Conference_Location

San Diego, CA

Print_ISBN

978-1-4244-3940-9

Electronic_ISBN

978-1-4244-2831-1

Type

conf

DOI

10.1109/SMIC.2009.4770525

Filename

4770525